Edited by Robert Repas
The generally accepted main goal of electrostatic-discharge (ESD) protection is to provide a low-resistance shunt path to ground (GND) for unwanted voltage spikes. A key to how well such measures serve their purpose is its dynamic-resistance figure used in the selection process. Fortunately, there are well-known ways to calculate the effective dynamic-resistance that protection devices, such as polymeric ESD suppressors or silicon-diode arrays, exhibit during an ESD transient.
Logic dictates that the device with the lowest dynamic resistance should give the best chance of dissipating spikes. But sometimes it doesn’t. All is not lost, however, as several techniques help boost the level of ESD protection.
The standard ESD pulse shape is defined by IEC61000-4-2. It specifies an initial current spike with a peak voltage of 2,000 to 8,000 V and a rise time of 0.7 to 1.0 nsec. Current level is rated at 3.75 A/kV at the peak voltage, or 30 A for an 8-kV voltage test. Current levels at 30 and 60 nsec are also specified at 2 A/kV and 1 A/kV, respectively.
This presents a special challenge to many modern electronic products built with state-of-the-art chipsets that use construction technologies well below 130 nm. These technologies poorly tolerate any dc voltage over 3.3 V, so an ESD pulse can be catastrophic for such a device. Furthermore, chipmakers have reduced onboard or on-chip ESD protection to 500 V, well below the typical field requirement of 8 kV.
Board designers not only need external ESD protection, but also need to make sure it’s robust enough to protect small-geometry chipsets. Just placing an 8-kV rated ESD protection device on the data lines or I/O pins being protected does not guarantee the chip set itself will pass an 8 kV in-system test.
Board layout and device location are crucial for effective protection from ESD. To that end, the designer must understand the effects that parasitic inductances have at the board level. For example, an 8-kV ESD strike at the test specification of 30 A through a printed-circuit board (PCB) trace with just 1-nH inductance generates a 30-V spike on that trace. This voltage is calculated using the equation:
VL, parasitic = Lparasitic × di/dt
where Lparasitic is the parasitic inductance of the trace and VL, parasitic is the voltage developed across it with the change in current over time, di/dt.
In looking at a typical circuit-board layout, the input trace circuit can be divided into four separate areas: the trace from the input to the junction of the ESD device (Lport), the trace from the ESD junction to the input of the IC (LIC), the trace from the junction of the ESD device to the device itself (LESD), and the trace from the ESD device to ground (LGND). These four parasitic inductances, LESD, LGND, LIC, and Lport, must be considered when deciding on the placement of the ESD device. LESD and LGND tend to raise the clamping voltage (VIC) while LIC and Lport work to the designer’s advantage to lower VIC.
Shorten traces to lower LESD and LGND
Sometimes a board’s layout prevents an ESD device being placed directly atop the PCB trace. Reasons vary, but placing an ESD component even 1 cm away from the data line being protected can ultimately translate into tens of volts on the device. The same is true for ground (GND) buses. In some designs the ESD device GND must pass through multiple vias and may even take a circuitous path to reach the GND plane. Both of these inductances create voltage spikes in addition to the voltage created by the ESD current flowing through the ESD device given by VESD = Ipeak × Rdynamic, where VESD is the voltage drop across the ESD device, Ipeak is the peak current of the electrostatic event, and Rdynamic is the resistance of the ESD device as it conducts.
The following simplified examples show how LESD and LGND affect VIC. Common PCB manufacturing processes give approximately 3 nH/cm for typical microstrip traces assuming certain widths, thicknesses, and dielectric constants. With that in mind, assume an 8kV ESD pulse is applied to the input of the I/O pin. The ESD device has a 1-Ω dynamic resistance. The first layout assumes both LESD and LGND equal 1.5 nH (0.5-cm spacing):
VIC = (LESD + LGND) × di/dt + Ipeak × Rdynamic
VIC = (1.5 nH + 1.5 nH) × 30 A/1 nsec + 30 A × 1.0 Ω
= 120 V
The second layout doubles the length of the traces, so each become 1-cm long for 3-nH each:
VIC = (3 nH + 3 nH) × 30 A/1 nsec + 30 A × 1.0 Ω
= 210 V
This example shows that lengthening the ESD protector trace from 0.5 to 1 cm increases VIC by 75%! So the rule is to keep the traces connecting the ESD protector as short as possible.
Shrink the ratio of Lport to LIC
Often datasheets for ESD protectors recommend putting the device as close as possible to the point of ESD entry. Manufacturers do this so the ratio of Lport to LIC is as small as possible (LIC >> Lport). The inductance of Lport will not necessarily affect the overall ESD performance but the inductance of LIC most certainly will.
The nonlinearity of LIC acts as a buffer to the initial peak of the ESD current pulse. This creates a substantial voltage drop toward the IC. This inductance gets smaller the closer the ESD device gets to the IC, and the voltage drop shrinks to the point where it provides no additional advantage. So it’s in the designer’s interest to make the ratio of Lport to LIC as small as possible to take advantage of the parasitic nature of the PCB trace.
Use of LIC and Lport is a straightforward way to improve overall ESD performance. However, there are designs that will still fail prematurely no matter how low the aforementioned ratio. In other words, the value of LIC does not sufficiently buffer the peak ESD current.
Adding a buffer resistor
One problem with the previous techniques is that the on-chip ESD structures can see too much current. They then become damaged, shorting the I/O to GND or VCC.
The ESD protector and the IC being protected actually share current from an ESD pulse. For example, a positive ESD pulse lets the protection device take the majority of the current, but some current travels into the IC and is routed out the VCC terminal. The overall circuit forms a resistive current divider between the ESD protector and the IC.
The rail diode on the IC is responsible for steering the remaining or “let-through” current into VCC where it returns to GND through a bypass capacitor. It’s difficult to determine the equivalent resistance for the IC’s ESD protection, but it’s undoubtedly higher than the on-board ESD device. For example, if the resistance of the on-chip protection (Rchip) is 10 Ω, and the Rdynamic for the external ESD protector is 1 Ω, the peak current seen by the IC is:
IIC = Ipeak * Rdynamic/(Rdynamic + Rchip)
IIC = 30 A * 1 Ω/(1 Ω + 10Ω) = 2.73 A
Resistors added in series between the external ESD device and the IC help lower peak current flow into the IC. For this example, adding a 10-Ω buffer resistance (Rbuffer) reduces the peak current flowing into the IC by almost 50%.
IIC = Ipeak * Rdynamic/(Rdynamic + Rbuffer + Rchip)
IIC = 30 A * 1 Ω/(1 Ω + 10Ω + 10 Ω) = 1.43 A
Obviously, a resistance beyond 10 Ω would further reduce the let-through current. The details of the appLICation determines the maximum resistance permitted.
Care must be taken when employing this technique in some of the high-speed appLICations such as high-definition multimedia interface (HDMITM) and USB 3.0. The Rbuffer resistor could disturb the line impedance and attenuate the signal beyond the standards’ compliance specifications. Careful board design can compensate for any ill effects. Nevertheless, board designers should keep this technique in their toolbox and apply it in situations where the board or in-system ESD level falls below their requirement.
Four simple steps to success
The ESD protection device alone may not be enough to protect modern chip sets from ESD transients. Fortunately, board designers can use these four strategies to optimize ESD protection:
1. Reduce the length of the parasitic stub trace or LESD.
2. Reduce the length of the GND trace and/or number of vias used to decrease LGND.
3. Make the ratio of Lport to LIC as small as possible on a given design.
4. Use buffering resistors between the ESD device and IC if the above are still insufficient.
All these practices reduce the voltage seen by the IC, as well as limit the amount of current the on-chip ESD structures must handle. Following these simple rules will give the board designer a more robust ESD solution that exceeds industry standards.