In 1965 physicist Gordon Moore predicted circuit transistor counts would double every 18 months. So far, of course, he’s been right. However, as billion-transistor microprocessors and miniature wristwatch TVs loom on the horizon, a new challenge emerges — packaging.
Packaging, by this definition and in broad terms, includes the housing of all passive and active circuit elements as well as the printedcircuit boards (PCBs) they mount to. Today, boards have more ICs crammed into less area than ever before. One reason is the advent of space-efficient chip-scale packages (CSPs). It’s generally agreed that CSPs are no more than 1.2-times larger than the IC silicon die itself. In contrast, a conventional package can be several times bigger than its die.
In a nutshell, chip packages connect microscopic silicon-die-based circuitry to macroscopic external leads for solder to PCB traces. Leads act both as a mechanical attachment and an electrical conduit. Earlier ICs, such as the ubiquitous dual-inlinepackages (DIPs), have vertical pinouts for connection to metal-plated holes. When DIPs were first introduced, most boards had electrical traces on just their top and bottom surfaces. But modern sandwich-style boards may have up to eight trace layers separated by insulation.
A more appropriate attachment for sandwich boards is called surface mounting. Instead of having leads insert into holes, they instead attach to conductive pads on the board surface. These pads may connect to subsurface traces through conductive vias. No longer limited to just two surfaces, sandwich boards permit more connections with only a slight thickness penalty. The shift towards surface mount technology and away from through-hole methods is probably the most significant trend in PC board design.
Surface-mount ICs were first invented about three decades ago at IBM. Their socalled controlled collapse chip connection (C4) flip chip is still considered one of the most efficient packaging schemes to date. Flip chips were the first chip-scale packages. In fact, some flip chips have no package whatsoever. These are bare-die ICs that mount circuit-side down on a PCB surface. Tiny high-temperature solder balls attach the IC’s aluminum contacts to conductive board pads.
Before mounting, solder paste is transferstamped to solder balls. This paste is actually a combination of low-temperature solder alloy and flux. Next, pick-and-place equipment locates an IC on board pads. Heated air directed at the paste layer causes it to reflow or melt momentarily. Use of a reflow oven is an alternative method. Surface tension in molten solder paste causes chips to self-align with the pads. The relatively higher-melt-point solder balls mostly retain their shape during the process which sets chip-to-board spacing.
After soldering, the assembly is cleaned with solvent to remove paste residue. Finally, injected beneath the IC is a polymeric underfill material or so-called interposer. This interposer serves three purposes. First, it acts as a barrier to foreign objects that may otherwise damage or short sensitive circuitry. Second, it provides an efficient path to dissipate heat. Lastly, it helps null CTE mismatch between board material and silicon. Without underfill, thermal cycling can damage solder connections or the die itself. With underfill, the attachment can survive several thousand 0 to 100°C temperature cycles. The bonds tend to be so good that it makes rework nearly impossible. “Once solder-bumped bare ICs are mounted, they can’t be removed. The high temperatures required to soften underfill material and free solder joints can irreparably damage circuit boards,” explains John Riley of The Institute of Interconnecting and Packaging Electronic Circuits (IPC), Northbrook, Ill. IPC is a 40-year-old trade association serving designers, board manufacturers, assembly companies, suppliers, and OEMs.
A major concern of using these so-called direct-chip attachments (DCAs) is the availability of known good die (100% electrically inspected). Burn-in testing of bare die is often done after attachment to boards and then it’s too late.
Addressing this rework issue is a studbump- bonding attachment from Panasonic Factory Automation Co., Franklin, Ill. Instead of solder paste, bump-equipped die attach to board pads with special conductive epoxy. After this nonhardening resin cures, the circuit undergoes electrical testing. If defective, the die can be removed at room temperature without damage to the board. If it passes, a heat-curable underfill is added which provides the mechanical attachment.
The inherent low profile of flip chips makes them ideal for height-constrained applications such as RF-circuitry in portable communications. The tiny solder ball connectors exhibit minimal parasitic losses. Still, flip chips and most other DCAs have certain limitations. One concern is that bare die are extremely fragile and can require special handling. Another limitation concerns solder bumps, which attach to dies where needed. In other words, bump patterns can differ depending on chip function. This requires that new boards be made each time IC design changes. The re-routing of traces takes valuable time and adds tooling and setup costs. For these reasons, DCAs and high-production-rate contract manufacturing don’t always mix.
OUTSOURCING VERSUS VERTICAL INTEGRATION
When IBM first introduced C4, vertical integration was commonplace. In other words, it wasn’t unusual for companies to build entire products from the ground up. Today, however, many OEMs source semiconductor die from outside vendors and rely on electronic manufacturing service (EMS) companies for assembly. This is one reason the EMS market continues to grow 20% per year and is expected to reach $50 billion by 2000.
To keep up, EMS companies such as Flextronics International, San Jose, continue to invest heavily in the latest equipment. Besides having high-production capability, such firms offer engineering expertise as well. Collaboration is necessary as product life cycles compress and OEM engineering staffs shrink. Time-to-market is even more critical these days especially in fast-paced consumer sectors.
And it’s in these instances that companies often opt for more commodity grade components and assembly processes. Considered by many as the workhorse of chip packages is the ubiquitous surface-mount quad-flat pack (QFP). Such packages have pinouts on all four edges, hence the name. Some QFPs contain upwards of 240 pins, or 60 per side. These leads can be on the order of 0.001-in. wide spaced only slighter wider than the leads themselves. Leads tend to be fragile and present to assemblers numerous challenges such as alignment sensitivity and solder bridging. Because leads extend beyond the package, QFPs take up a lot of board area. Despite these limitations, and concerns they’re nearing capacity limits, QFPs are reworkable and most likely here to stay, remarks IPC’s Riley.
BALL GRID ARRAYS
As QFPs begin to show their age, a relatively new attachment method called ballgrid array (BGA) is taking hold. BGAs can be thought of as a cross between DCAs and conventional surface mount packages. BGAs attach with symmetrically spaced solder balls located directly beneath the IC. This configuration takes up less board space than QFBs and provides deck heights nearly on par with flip chips. And BGAs self-align just like DCAs. Moreover, balls are spaced further apart than pins on QFPs with equal I/O counts. These features make BGAs attractive for mass-produced consumer products.
The BGA format also happens to work well in chip-scale size. Several companies have introduced or are working on some 50 different CSP designs including BGAs. At present, the de-facto standard comes from Tessera Inc., San Jose. Its CSP, dubbed μBGA, joins and interconnects silicon die ICs to a thin, flexible-film ball grid. This grid is fixed atop the IC with a compliant, adhesive elastomer which doubles as underfill. Such a configuration lets the devices mount on standard PCBs using regular pick-and-place equipment. Because the underfill stays with the chip, μBGAs are reworkable. And unlike bare die, the package can be socketed for electrical testing prior to installation.
One shortcoming of such designs, however, is that it’s impossible to visually inspect solder joints of an installed chip because the view is blocked by the IC itself. Assemblers must instead use X-ray imaging for inspection. Yet another detractor is cost. The polyimide film used to make the flexible grids is in short supply these days and tends to be expensive. Cost per I/O for μBGAs can be roughly twice that of conventional thinsmall- outline packages (TSOPs).
On the plus side, μBGAs can use the same package base to house a variety of circuit types such as DRAM and flash memory. For example, Intel recently obtained a license to use the package for its new Rambus memory modules. Tessera says it has completed several ASIC designs as well, some with I/O counts exceeding 600.
But chip-scale BGAs aren’t limited to complex circuits such as these. For example, Dallas Semiconductor, Dallas, recently announced it’s producing one-wire chips in pin-head-sized packages. The “package” in this case is a thin polymeric coating. The ICs come in a variety of types including EPROMs, RAM, and digital thermometers. Despite their tiny size, Michael Bolan, vice president of product development for the project, expects big things from the new chips. Because each one-wire chip contains a unique digital address, objects containing the ICs can be made specifiable over the Web. This never-duplicated registration number also makes it possible to have several chips communicate over the same twisted pair. This so-called MicroLAN could help bring inexpensive distributed temperature sensing, and remote monitoring.
RACE FOR A STANDARD
As companies jockey for position in the chip-scale race, it’s unclear which technology will become most widely used. Some say CSPs are just a stepping stone to even more exotic flip chip and bare die technologies. Other studies predict flip chips will gain ground over all BGAs, while QFPs chug along and slow. BGA-CSPs appear to have a near-term edge, but ultimately, economics will decide the winner.