From the palm of the hand to the backbone of the factory

Crack open a cell phone or a handheld computer and you are likely to find a processor based on either a MIPS or ARM design. These two families have been the architectures of choice for a wide variety of portable applications where low power consumption is a priority. MIPS, for example, claims it is the most widely licensed 32 and 64-bit architecture in the world.

Processors in these two families have also handled computational tasks well enough to power data-intensive jobs such as laser printing and video gaming. Such capabilities have not gone unnoticed among developers of industrial applications. ARM and MIPS processors now also power motion controllers, operator terminals, automatic teller machines, and numerous other items.

Both ARM in Cambridge, U.K., and MIPS Technologies Inc., Mountain View, Calif., recently have updated their designs to better handle multimedia applications. Premier uses envisioned for these processors tend toward portable Internet appliances, game boxes, and third-generation cell phones. Nevertheless, such processors promise to find a home in industrial applications where video or similar data-intensive tasks crop up.

For example, ARM has added single-instruction multiple-data stream (SIMD) instructions to its v6 processor scheduled to be available in microprocessor cores this year. (SIMD is a computer architecture that performs one operation on multiple sets of data.) The feature is meant to better handle video and multimedia as foreseen on new cell phones and PDAs. ARM says the SIMD instructions boost the performance of audio and video functions by as much as a factor of four compared to its earlier processors.

Such facilities also let the new processor work better in systems containing other processors, and specifically with digital signal processors (DSPs). The approach envisioned for many applications would be to handle communications via a low-power ARM and update the DSP or other another companion chip as required for processing multimedia data streams. The benefit of adopting the dualprocessor approach is not just raw performance. It is viewed as a way of accommodating frequently changing multimedia standards.

Mixed endian support is another development aimed at facilitating multiprocessor setups. Endian refers to the order of bytes in a computer word. Big endian is the normal order with the most significant byte or digits placed leftmost in the structure. Some CPUs, most notably Intel CPUs, deal with words in little endian order, with the least significant digits on the left.

The v6 ARM design will handle both big and little endian words by means of new instructions. One reason to provide such facilities is that widely used interfaces such as PCI, CardBus, and USB are little endian. But applications characterized by large files (such as MPEG images and Java-enabled Web pages) are big endian.

Recent enhancements to the MIPS32 and MIPS64 microprocessor Risc architectures have similar aims. The first implementation is in an ultralow power CPU core occupying less than a half-millimeter of silicon. An endianswap instruction will interchange bytes within a register, which improves efficiency for multiprotocol processing. New rotate instructions will also do the same register operation on bits. These are expected to be especially useful in checksum and encryption algorithms.

Texas Instruments Inc. is one of the first companies to license the MIPS32 4KEc synthesizable core. TI will integrate the 4KEc core with its digital signal processing (DSP) technology to better handle multimedia and security applications for DSL, cable, and voice-over-Internet protocol (VoIP). The end result will be home routers, integratedaccess devices and voice-over-broadband gateways for streaming audio/visual, real-time video conferencing, and similar high-data-rate services.

MIPS also enhanced memory-management capabilities to better handle smart mobile devices and other applications where memory is relatively small. This is the reason its processors can now manage pages as small as 1 kbyte. Pages can also be as large as 256 Mbyte to better handle the passing of large chunks of data over networks. The latter capability will, among other things, reduce the number of times the processor must go off the current memory page to get data for calculations, thus boosting determinism and efficiency.

The new MIPS designs support the use of coprocessors as well. The point is to more easily combine 64-bit floating-point units with 32-bit CPUs, thereby reducing the cost of handling computationally intense applications. This strategy, says MIPS, also provides a clear path for uses likely to employ 64-bit processors in the future.

Memory cache handling is another area that has drawn the attention of processor architects. Memory hierarchies have grown increasingly complex, and newer processors have begun incorporating features to better manage the various levels of memory likely to crop up in more complicated systems. One way MIPS addresses this need is to include a mechanism that indicates the presence of L2 and L3 caches. (As a quick review, L1 cache is a memory bank built into the CPU chip. L2 and L3 cache is secondary staging that feeds the L1 cache. L2 may be built into the CPU chip, reside on a separate chip, or on a separate bank of chips. L3 is generally on separate chips.)

NOT LOST IN THE TRANSLATION
It soon may become easier to adapt code written for one brand of embedded processor to run on another. That is the promise of new technology from Transitive Technologies Ltd. in San Diego. The firm has developed software that lets applications developed for ARM processors run on MIPS products. Moreover, the company says this takes place without porting and without degrading software performance.

The Transitive software is called Dynamite. The company likens it to a virtual CPU. Through a patent-pending process, it translates binary code for one processor into that for another. In the process, it also dynamically optimizes the resulting object code, but without the need for recompiling.

The Dynamite program is designed as four sections. A front-end module accepts source code from a specific processor and turns it into an intermediate code. This feeds into a kernel that analyzes and optimizes the code for efficiency. Its output goes to a back-end module that uses the data to generate binary for the target system. There is also a separate module called a harness that initializes the Dynamite program by defining optimization levels, assigning memory locations, and so forth.

Dividing the software into modules allows for the possibility of using multiple front-end modules feeding one back-end module. This would let a processor running Dynamite use programs written for more than one other brand of CPU.

Dynamite optimizes code by exploiting the idea that most application programs have hot spots — sections that execute frequently. Dynamite closely scrutinizes these sections for ways of speeding up execution. It also contains methods for eliminating branching code and unused portions of translated programs.

The current implementation of Dynamite runs on Linux but future versions will support WinCE as well as other embedded operating systems. By the second half of this year, Transitive expects to have front-ends and back-ends for most major architecture combinations operating at native speed or better. The first realization of an ARM-to-MIPS engine is from Alchemy Semiconductor Inc. The Austin, Tex., company licensed the Transitive technology to produce a family of MIPS processors and evaluation platforms that include a 400-MHz, half-watt Au1000 and a PCI-enabled device called the Au1500.

JUICED ON JAVA
Display graphics are increasingly important in a variety of embedded applications. The trend is having an impact on operating systems designed for these uses. One development in this area is an OS that aims to simplify the task of designing Java applications for embedded processors.

The XE 1.0 operating system comes from SavaJe Technologies Inc., North Chelmsford, Mass. SavaJe is a spin-off from Lucent Technologies. Typical applications for the operating system, says the company, are expected to include smart phones, PDAs, and home servers.

The software can port to any ARM-based processor running at 150 MHz or better. It sits in about 32 Mbytes of ROM and works with systems having a minimum randomaccess memory of 32 Mbytes and 12 Mbytes of nonvolatile storage.

The XE operating system incorporates software technology called Jazelle made by ARM itself. Jazelle accelerates Java performance on the XE platform when running graphic-intensive applications such as games. It is expected to bring similar benefits to industrial applications where the trend is toward human interfaces with ever more complex graphics.

SavaJe claims that its operating system now runs Java apps from 5 to 15 times faster than those running on Java virtual machines for existing operating systems. As such, Jazelle technology lets devices execute Java byte codes directly. Consequently, Java apps execute perhaps 10 times faster than on processors where byte codes must first pass through a Java compiler (For a quick review of Java concepts, see Java on a Chip, MACHINE DESIGN, 9/23/99, pg. 88.).

XE is set up so that developers can integrate it relatively easily with software modules. The usual method would be to either recompile application source code with the operating system kernel, or to link the binary form of the module directly into the kernel.

A similar philosophy of components can be found in a version of Microsoft's Embedded Windows XP operating system that targets cash registers, ATMs, and similar devices. The operating system is due out in the second half of this year. It is more comprehensive than NT 4.0 Embedded, consisting of about 10,000 software components compared to about 300 in the older operating system. XP Embedded is said to support Internet and multimedia technologies such as DirectX graphic tools, as well as Windows Media audio and video formats.

XP Embedded contrasts with Windows CE, an embedded operating system specifically designed for small or mobile devices like cell phones and handheld computers. The newest version of CE, currently in beta test, is called Windows CE .NET. Features are said to include support for wireless technologies such as Bluetooth.