By Tom Glenn
Vice President,
New Package Concepts
Steven Webster
Product Manager
Sensor Products
Amkor Technology
Chandler, Ariz.

EDITED BY LAWRENCE KREN

SOIC package (thicker than standard because of silicon  cap and gel-coat)

SOIC package (thicker than standard because of silicon cap and gel-coat)


Microelectromechanical systems (MEMS) find use in a rapidly growing number of products including inkjet print heads, implantable medical dispensers, accelerometers, and pressure sensors. Key to broader adoption of the technology is packaging

A package, by this definition, is a device that protects MEMS and ICs from damage and contamination. There are two basic packaging approaches. The first installs a separate package on each MEMS unit after die singulation. Die singulation means to slice individual devices (die) from the wafer from which they were deposited or etched. Packaging after singulation is mostly used for prototyping and low-volume production. Another approach better suited for high production adds the package before singulation. There are many variations on this theme.

CAP WAFERS
Cap wafers protect die wafers before singulation and offer economies of scale when MEMS process yields are sufficiently high. Here, a silicon cover wafer, etched to match MEMS die located on another wafer below, is bonded on top. Bonding two wafers hermetically — within a vacuum or inert gas atmosphere — makes it possible to encapsulate a micromachine before die singulation. Yields of 80% or better are possible because the procedure is done when wafers are the cleanest and environmental contamination the lowest. Encapsulation, however, does nothing to prevent process-related defects.

After wafer bonding, encapsulated MEMS devices can be packaged similar to conventional ICs, but with a few added complications. For one thing, silicon caps add significant thickness to a package. A typical MEMS-cap stack-up, for example, is about 120 mils or more. By comparison, relatively older package technologies such as SOIC are only about 80 mils thick. And excessive package height is undesirable for emerging portable devices that demand components with slim profiles.

Another drawback to silicon caps, depending on their geometry, is they may not tolerate thermal stresses from assembly and package encapsulation as can conventional ICs which are nearly monolithic. Stresses to 250,000 psi at the back side of a MEMS chip from curing die-attach epoxy will literally crush the device. And, it's been shown that only 0.1-mil distortion can fracture protective silicon caps as well. One way to reduce thermal stress in silicon capped MEMS die is to coat them with a compliant protective layer such as silicone gel coat.

CERAMIC PACKAGES WITH CAVITIES
Cavity packages for ceramic-based MEMS must have mechanical properties that closely match those of the MEMS device itself. For example, surface-acoustic wave (SAW) filters — piezoelectric devices that work off vibration of a quartz or lithium niobate structure — typically use a silicone die-attach material. Similarly, especially fragile ceramic MEMS require special handling and temperature control during processing to limit stresses. Packages with ceramic substrates improve rigidity but cost more than organic substrates. There are several ceramic-cavity packages with standard pinouts to choose from.

The most economical of these is the familiar dual-inline package (DIP). A variation on a DIP termed ceramic dual-inline package (CERDIP), uses high temperatures (about 430°C) to seal by means of a dry-press process. The approach offers relatively low-cost assembly after tooling is amortized although it has some shortcomings. For example, the elevated temperatures inherent to the process can damage sensitive circuits. CERDIPs also require through-hole mounting which costs more than surface mounting. On the other hand, material for surface-mount ceramic packages such as SOIC, PQFP, or PLCC, cost more, offsetting the savings that might be gained from easier assembly. Here, custom tooling and brazing or other relatively expensive semimanual, lead-attach methods boost cost. Alternatively, solder-seal ceramic packages are available for both through hole and surface mounting. These require sealing temperatures of only 320°C. It is also possible to use an epoxy seal which lowers maximum curing temperatures to 150°C.

A recent development in ceramic packaging technology are chip-size packages with a form factor similar to a PLCC. They are constructed in arrays and snapped apart (singulated) rather than sawed. These packages tend to be small and are generally less expensive than leaded packages. And they can be sealed with gold, tin, soft solder, or epoxy.

PLASTIC CAVITY PACKAGES
It is also possible to produce premolded plastic cavity-and-lid packages that otherwise resemble conventional post-molded IC packages. These are often plated with a flash coating of gold to allow wire bonding and solder-dip board assembly. To keep temperatures below 150°C, some premolded packages require the use of a high-frequency wire bonder to attach gold or aluminum wires between the MEMS bond pads and leadframes.

Premolded plastic packages are made by either injection molding or transfer molding. But injection molding is favored over transfer molding because injectionmolded products better resist moisture. Despite being made of low-cost materials, plastic packages tend to be more expensive than ceramic because they require custom tooling. However, sufficiently high-production volumes may make it possible to recover tooling cost. Currently, liquid-crystal polymers offer the best price-performance quotient because of their thermal, rather than optical properties.

Another recent packaging option surrounds the MEMS device with a cavity or dam made from epoxy. The dam is topped with a simple lid of plastic, aluminum, or ceramic. Because lids don't require forming, such packages are relatively inexpensive. Molding them in a matrix format further cuts cost.

MEMS too delicate for plastic molding but still somewhat rugged can be protected with a liquid encapsulant. Liquids don't exert as much pressure on the device as plastic molding. This makes possible the use of a Chiparray or Snaparray style packages. Both of these packages are near chip-scale size, are assembled in matrices, and are often less expensive than premolded types. They can be surface mounted and formed with land-grid array, ball-grid array, or LCC footprints.

ALWAYS TRADE-OFFS
Ideally, a MEMS package should be inexpensive, able to be handled by existing automated board assembly machinery, and protect the electromechanical device against contamination. When the micromachined die is rugged and the application allows standard packages, packaging cost and availability is the same as for conventional ICs. Then, choice of package style is based on device size, application, and cost, only.

However, when the application deviates from standard volume-assembly processes, including die coating, molding, or package height, costs will be higher. But, if some custom steps in packaging mean that the MEMS manufacturer can reduce wafer fab cost, it may be a fair trade-off. Truly rugged MEMS devices can be packaged in more or less "standard," low-cost, semiconductor-IC molded packages. For less-robust MEMS not able to withstand molding stresses, packages can be augmented with a relieving gel coat or built using a lower stress encapsulation method. Sealing options for cavity packages include hermetic glass, solder, or liquid encapsulant. Here again, the choice is a compromise between required performance and cost.

PACKAGING ACRONYMS AND DESCRIPTIONS
Small outline integrated circuit (SOIC): SOICs are molded plastic surface-mount packages with leads on two sides only. They are available with 8 to 44 leads and body widths from 150 to 525 mils. SOICs have "gull-wing" metal leads; a variation called the SOJ package has inward-turning J-shaped leads that permit a smaller footprint.
Ceramic dual-inline package (CERDIP): CERDIPs use the DIP through-hole mounting arrangement. They provide up to 24 leads on 300-mil wide packages; up to 48 on 600-mil packages.
Plastic quad flat pack (PQFP); Plastic leadless chip carrier (PLCC): Both packages have leads around their entire perimeters. PQFP is the gull-wing version and PLCC, the J-lead. PQFPs have up to 256 leads and body sizes to 28-mm square. PLCCs have 20 to 84 leads and body sizes from 0.352-in. square to 1.152-in. square. (Mixed metric and Imperial body size measurements in the packaging industry are a legacy of evolving standards development.)
Chiparray and Snaparray: Both are high pin-count packages assembled in strips or arrays to ease handling and testing. Like other advanced packages, they differ from the older package types mentioned in the article in that the active device is mounted on a square of rigid or flexible circuit board material, rather than on a metal leadframe. This permits higher pin counts because electrical connections can be arranged in two-dimensional arrays on the package bottom instead of peripherally.