FPGAs shorten reaction times in motion controls.
National Instruments Corp.
The quest for better throughput, faster changeover times, and less waste and downtimes has made machine-automation systems more complicated. Besides handling logic or process controls, systems today need to provide predictive maintenance, intelligent fault handling, fast response, and run control algorithms that are possibly custom made. Features like these are difficult to implement with traditional PLCs. One way to get around the problem combines embedded control systems with PLC technologies.
PLCs typically operate according to the IEC-61131-3 specification. This specification details guidelines for operating-system execution, data definitions, programming languages, and instruction sets. Unlike the PC world, where one C program works well on any computer, every PLC vendor has its own flavor of IEC 61131-3 compliant specifications. But all brands have a basic architecture that is similar.
A look at how a PLC operates illustrates the similarities. For example, to turn on an LED, any PLC needs three components: the program logic, the memory map, and the I/O scan. When the program logic lights the LED, it writes a True bit value to a variable called LEDValue. This variable resides at a specific location in the PLC memory map. The I/O scan gets the True value from the memory map and transfers it to the physical I/O line, turning on the LED. The program logic never directly controls the I/O line. The memory map acts as a buffer between program logic and the I/O. It is the responsibility of the I/O scan to transfer the values in the memory map to the I/O.
The isolation of program logic from I/O by the memory map makes a variety of actions possible. For example, troubleshooting technicians can force I/O bits on or off in the memory map when debugging a system. Or they can update a program in the field on the fly while the I/O scan is running. However, programmers must also watch out for blocking functions that may halt the program logic indefinitely. Blocking functions, as the name implies, are logic sequences that prevent a program from completing its execution. A typical example is a program loop waiting for a specific input value before continuing.
The scanning-type architecture of PLCs is excellent for controlling sequential processes. However, modern machines are, by nature, more complex and more reactive than simple sequence logic alone can handle. For example, a typical packaging machine today devotes 20% of its program to the logic for normal operation. The remaining 80% deals with fault and exception handling. Controls for such complex machines need a combination of sequential and reactive programming architectures.
Programmable-automation controllers (PACs), such as the CompactRIO from National Instruments, use embedded technologies for implementing reactive architectures. In the CompactRIO the embedded portion takes the form of a field-programmable gate array, or FPGA. FPGA chips contain thousands of logic gates that interconnect via programming to create specific logic patterns or functions. The reprogramming of an FPGA is equivalent to rewiring the chip circuitry to perform different tasks.
Most PACs also incorporate a floating-point processor in addition to the FPGA. The floating-point processor runs a real-time operating system that handles sequential tasks, similar to those run by a PLC. PACs combine the best of embedded control and PLC technologies to produce an architecture optimized for programming complex machines.
The goal of using FPGAs is to create control systems that incorporate reactive behavior and respond quickly. Engineers often used FPGAs inside industrial-control products, but they typically did not have access to internal FPGA operations. The programming of FPGAs historically required expertise in hardware description language (HDL) or in complex design tools more familiar to hardware designers than to industrial-control engineers.
On the other hand, the CompactRIO PAC uses National Instruments LabView as its programming language. LabView is a high-level graphical-development environment designed specifically for measurement and control. Lab-View configures the custom circuitry inside the FPGA so a CompactRIO can rapidly process and deterministically generate synchronized analog and digital signals. The PLC architecture has trouble reproducing this behavior or does so only with the help of add-on modules. With an FPGA, it's possible to execute digital logic at 20 MHz, analog closed-loop control at 1 MHz, and update servoloops at 200 kHz/axis for motion control.
When LabView develops code for an FPGA-based device, it displays only those functions the FPGA implements. The palette of functions for LabView's FPGA Module includes such typical Lab-View functions as while-loops, for-next loops, case structures, and sequence structures. Also included is a dedicated set of FPGA-specific functions for math, signal generation, and analysis; linear and non-linear control; comparison logic, array, and cluster manipulation; occurrences; analog and digital I/O; and timing. Developers combine these functions to define the logic and embedded intelligence for any FPGA-based device.
LabView programming takes the form of block diagrams that make it easy to follow the data flow and aids in understanding how the program behaves. Unlike traditional PC or PLC processors, FPGAs are parallel processors. So adding additional loops to a program does not degrade the performance of other independent loops. For example, independent counter and PID loops in the same FPGA execute in parallel. All tasks take place at the same time. There is no task suspension while another task runs, nor any latency in switching between multiple tasks as in PLCs or PCs.
The PID function block is just one example of intellectual property (IP) available for programming FPGAs in LabView. There are a variety of sources for signal-processing IP that target high-speed monitoring and control applications. The NI SoftMotion Development Module includes enhanced algorithms for motion control and built-in inputs for numerous feedback devices including quadrature encoders. The NI Digital Filter Design Toolkit provides functions and interactive tools for design, analysis, and implementation of digital filters within the FPGA.
Recall that PACs typically combine a floating-point processor with an FPGA running logic in hardware. LabView Real-Time creates software that executes on the floating-point processor and communicates with the FPGA. Programs on the floating-point processor typically perform complex floating-point calculations, data logging, networking, e-mail, file-transfer protocol (FTP), remote web control, and any operations that do not fit within the FPGA fabric.
There are tasks that demand special processing engines to handle functions beyond the scope of the FPGA. For example, the real-time environment of the PAC typically handles floating-point arithmetic, including spectral analysis or custom control algorithms. Some systems even transfer the data to a Windows host computer for off-line analysis, data logging, or user-interface displays.
FPGA-based devices use flash memory to store compiled programs and run the application immediately after power-up. In this configuration, the FPGA program runs so long as the FPGA has power. And it continues to run even if the host computer crashes or is powered down. This working environment suits the task of programming safety power-down and power-up sequences that handle unexpected events.