Improvements in the deposition of copper will usher in new ultralarge-scale ICs.
Copper has become the material of choice for fabricating connections on ultralarge scale integrated circuits. The advantages of this technology are well chronicled. Copper has greater conductivity than aluminum interconnects it replaces, thus it engenders less I2R loss. Copper patterns also have less distributed capacitance than equivalent aluminum because they can be thinner. And they are less subject to electromigration, so copper lines are less likely than aluminum to grow thin under a current load.
The transition to copper reduces interconnection delays by about 30% compared to those fabricated from aluminum. This is particularly important in chips with feature dimensions smaller than 0.18 microns. At this scale, interconnects have a bigger impact on signal delay time than does the feature size of transistors. Specifically, signal delays caused by interconnections increase with the square of the reduction in feature size.
Researchers are continuing to perfect copper processes to handle dimensions below 0.13 m. New chemistries address problems associated with the first processes used to deposit copper interconnects. For example, voids can be inadvertently created when constructing copper vias between layers. There have been challenges in getting copper to build up in the proper proportions on the sides of the canallike trenches and holes that create connections between metal layers (vias).
The first chemistries used to create copper interconnects were similar to those devised for plating copper onto printedcircuit boards. Though these chemistries work well for PCBs, they are not tweaked to produce the submicroscopic dimensions found on chips. Specifically, there are impurities in ordinary copper chemistries for PCBs that can affect a silicon substrate in negative ways. These impurities also make it more difficult to measure the strength of other chemicals that are strategic to a successful deposition process.
New chemistries developed to address these difficulties come from the Polyclad Technologies operation of Enthone Inc. in New Haven, Conn. Its Enthone ViaForm process targets chips with features as small as 0.13 microns. It uses four components for controlling copper deposition: an electrolyte, accelerator, suppressor, and leveler. The electrolyte contains the copper, sulfuric acid, and chloride needed for copper deposition. The accelerator, suppressor, and leveler each consist of one ingredient.
A review of the dual damascene process used in depositing copper interconnects helps explain the role of the various chemicals. The "dual" part of the name refers to the depositing, in a single step, of both the copper vias passing between two layers and a single layer of copper connections. This contrasts with the older damascene (not dual) process where vias and the metal connections on each layer both required separate deposition steps. The damascene moniker arises from the use of layers and harkens back to an ancient glass-steel bonding technique.
A point to note is that copper gets deposited on a chip surface as a coating, usually through electrodeposition, a process analogous to plating. Next, excess copper is sanded or ground away through chemicalmechanical planarization (CMP) to leave the required patterns. (CMP is used instead of etching because copper can't be etched with current subtractive etching methods.)
The dual damascene process starts with the deposition of a thin silicon nitride layer on top of the first metal layer. The silicon nitride serves as a stop for the etching process. Atop the SiNx goes silicon dioxide dielectric. The SiO2 is then patterned for vias and etched down to the metal layer. Etching proceeds through the SiO2 and stops at the SiNx. Next comes the deposition of another thin SiNx layer and then more SiO2. The latter layer of dielectric gets patterned and etched for interconnections. The interconnection etch stops at the second SiNx layer.
Once holes for vias and trenches for connections have been etched, the process next deposits a thin film of tantalum nitride through physical vapor deposition (PVD), or sputtering. This acts as a barrier coating to keep the copper from bleeding into the silicon. The deposition of a copper seed layer, also usually through PVD, then provides a low-resistance conductive surface for the ensuing step. The balance of the copper gets added through electrochemical deposition.
The wafer then goes through CMP and thereafter gets coated with a cap of Si3N4 which acts as a sealer. Ensuing layers and vias then get added atop this structure in a similar fashion.
The copper-plating process takes place with the wafer exposed to a fountain of solution containing copper ions. Deposition equipment makes electrical contact with the seed layer of copper on the wafer. Current flows from a cathode to the wafer, causing a reaction, which results in copper being deposited on the wafer surface. Electrical current flowing to the wafer is proportional to the amount of metal deposited. A tool dispenses the electrolyte and other chemicals based on an algorithm that depends on the elapsed deposition time and current levels.
The accelerator and suppressor are organic chemicals that together help ensure that current densities during plating don't get too high. They are used in relatively low concentrations (a few grams/liter of electrolyte) and let copper fill the deep, narrow trenches on the chip reliably, without forming any voids.
Voids were a problem in the first generation of copper. They occur when current densities that are too high during plating cause copper to accumulate on the sharp edges of trenches at a faster rate than down in the trench itself. Eventually the effect can narrow the opening of the trench to the point of choking off accumulation beneath it. The result is a void in the trench. The leveler component of the chemistry also has an impact on current density during electrodeposition. It basically suppresses current somewhat in the area near dense-but-small SiO2 protrusions (as, for example, where the dielectric has been etched to hold multiple copper interconnections). The result is a relatively smooth surface of copper. This, in turn, limits that amount of copper that must be polished away during the CMP step.
If the leveler chemical was absent, there would be a dip in the copper material that gets deposited over large trenches and a deeper build-up over smaller but denser features. The result would be a surface needing a fair amount of CMP smoothing.
Use of copper adds complexity to the CMP step. One of the difficulties is that copper is softer than the tantalum diffusion barriers that surround it. This means that CMP can make the copper surface dish down unless special measures prevent this phenomenon.
Another problem is that copper particles ground or etched away during CMP can get lodged in the brushes that clean the wafer after the polishing step. It is also difficult to clean the minute copper particles out of these brushes completely. The brushes then become potential sources of contamination for wafers that get processed later on.
Fortunately new cleaning chemistries mitigate these effects.
Work is also progressing on copper processes able to handle dimensions on the order of 0.07 microns. Researchers at Enthone, for example, are studying ways of improving the deposition of the copper seed layer to handle trenches with smaller dimensions. Voids and defects in the seed layer become more of an issue at the smaller dimensions.
One technique that seems to hold promise in this regard is to substitute electrochemical deposition for PVD when creating the seed layer. Researchers at Enthone also say they are studying ways of repairing defects in already deposited seed layers. It is unlikely, they say, that defectfree seed layers can be created in a single step at these dimensions. It looks as though ensuing steps will be required to patch holes and fill voids.